Centre for Formal Design
and
Verification of Software
Esterel SCADE & Model Based Design Program

Principal participants:
IIT-Bombay, Esterel Technologies Ltd., BARC, NPCIL.


27/11/2009
09:00-09:30Registration
09:30-10:00Opening RemarksS.D. Dhodapkar, Outstanding Scientist(BARC)
Cyrille Fague, VP(Esterel Technologies)
10:00-10:30Tea
10:30-11:00 Synchronous Languages: SemanticsDr. A.K. Bhattacharjee(BARC)
11:00-12:00Basis of  SCADE synchronous language-IEsterel
12:00-13:00Basis of  SCADE synchronous language-IIEsterel
13:00-14:30Lunch
14:30-15:30Some recent trends in model checkingProf. S. Chakraborty (IITB)
15:30-16:00Tea
16:00-17:00Computation of quantitative timing properties of synchronous programs using Discrete Duration Calculus.Prof. P. Pandya (TIFR)
17:00-18:00Modeling & Verification Case StudiesEsterel

28/11/2009

09:30-10:30SCADE DisplayEsterel
10:30-11:00Tea
11:00-11:30SCADE compliance with IEC 60880 nuclear safely standardEsterel
11:30-12:00Case Studies from BARCBARC
12:00-12:30Case Studies from igcarIGCAR
12:30-13:00Case Studies from NPCILNPCIL
13:00-13:30Discussion
13:30-14:30Lunch
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